Business Wire

Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus, Delivering Best-in-class Productivity and Quality of Results

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence ® Cerebrus™ Intelligent Chip Explorer, a new machine learning (ML)-based tool ...
Business Wire

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput

Proven flow enhanced with unified placement and physical optimization engines used to complete hundreds of advanced-node tapeouts at 16nm to 5nm and below Industry’s first unified physical ...
Semiconductor Engineering

Hyper-Convergence Is The New Normal For Digital Implementation

The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet ...
Semiconductor Engineering

Low-Power IC Design Without Compromise

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA ...
EDN

Cadence Encounter Digital Implementation System 9.1: avoiding incorrect by construction

One of the most serious problems with design flows for 32 and 28nm designs, aside from the sheer complexity involved, is what you might think of as an impedance a mismatch between the flow and the ...