Traditional IC pattern-generation methods focus on detectingdefects at gate terminals or at interconnects. Unfortunately, a significantpopulation of defects may occur within an IC's gates, or cells.

CHARLOTTE, N.C. — The IC design and test community's quest to achieve fewer than 100 defective parts per million (DPPM) is becoming more difficult as process technologies move below 100 nanometers.

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

The industry is investing in more precise and productive inspection and testing to enable advanced packages and eventually, 3D ICs. The next generations of aerospace, automotive, smartphone, and ...

Semiconductor test equipment leader Chroma ATE announced that its founder and chairman, Leo Huang, will step down as CEO, handing the role over to I-Shih Tseng, the current president... Semiconductor ...