Breaking the 100M Token Limit: EverMind's MSA Architecture Achieves Efficient End-to-End Long-Term Memory for LLMs

The research introduces a novel memory architecture called MSA (Memory Sparse Attention). Through a combination of the Memory Sparse Attention mechanism, Document-wise RoPE for extreme context ...

Phison Rescales Local AI Inferencing with Flash Memory Expansion

Phison Electronics (8299TT), a global leader in NAND flash controllers and storage solutions, today announced its GTC ...

New memory architecture targets AI inference bottlenecks

Lightbits Labs Ltd. today is introducing a new architecture aimed at addressing one of the most stubborn bottlenecks in large-scale artificial intelligence inference: the growing mismatch between the ...

AI’s memory chip shortage is quietly taxing the entire economy

AI's insatiable appetite for memory chips is crowding out all other buyers — and the consequences will ripple through every ...
Nanowerk

Hydrogen-controlled AI semiconductor enables learning and memory in two-terminal device

A new neuromorphic device controls hydrogen ions to mimic synaptic learning and memory, achieved for the first time in a vertical two-terminal architecture.
Semiconductor Engineering

HBM4E Raises The Bar For AI Memory Bandwidth

The Rambus HBM4E memory controller extends a long-standing Rambus leadership position in HBM controller IP. Being first to ...
Semiconductor Engineering

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.