EDN

Tracking PLL design through the decades, part 1

PLLs (phase-locked loops) are among the most commontypes of analog/mixed-signal circuits on today’sSOC (system-on-chip) ICs. PLLs are essential companionsto the digital-logic circuits and processorson ...
Design-Reuse

How to design a better 1.5-V 2.4-GHz CMOS PLL for wireless applications

Since the VCO is one of the most important elements in the PLL system it is an appropriate place to begin this article, which addresses the challenges of designing a 1.5-V 2.4-GHz CMOS Phase Locked ...
Electronic Design

All-digital phase-locked loop offers sub-mW power consumption

The Intuitive Internet of Things, or I2oT, is a concept imec has been working to bring to fruition. Speaking at the imec Technical forum held in conjunction with SEMICON West 2015, Luc Van den hove, ...
Design-Reuse

A 66-mW 3.4Gbps Transmitter PHY for HDMI Applications in 2.5V 40-nm CMOS

This paper presents a low-power Synopsys® DesignWare® High Definition Multimedia Interface Transmitter (HDMI TX) PHY in a 2.5V 40-nm CMOS process. It employs a number of features for IP portability ...
EDN

Tracking PLL design through the decades, part 2

The desire to integrate more gateshas driven two advances in CMOS-processingtechnology, enabling the integrationof practical inductors in genericCMOS-logic processes. The first, theuse of CMP ...
Electronic Design

All digital phase-locked loop offers sub-mW power consumption

San Francisco, CA. At the 2017 International Solid-State Circuits Conference in San Francisco, imec, Holst Centre, and ROHM presented an all-digital phase-locked loop (ADPLL) for Internet-of-Things ...