GitHub

Single-Cycle MIPS Processor on Cyclone V (5CSEMA5)

This project implements a single-cycle MIPS-style processor in Verilog and deploys it on the Cyclone V FPGA (DE1-SoC, 5CSEMA5). The design includes a fully integrated datapath and control unit capable ...
IEEE

FPGA Based Voice Automated Cleaning Robot

Abstract: With increasing demand for smart home automation and reduced manual intervention in routine tasks, the need for efficient and voice-controlled cleaning systems has become vital. This work is ...
GitHub

ECE464/564 Final Project

This document contains the instructions and commands to setup ECE464/564 final project directory. In the folder tree of this project, several Makefiles are used to Once you have placed project2022.zip ...
IEEE

Hybrid VLSI Design for AES Cryptography with Pipelined Architecture

Abstract: The Advanced Encryption Standard (AES) cryptography hybrid VLSI architecture presented in this study is optimized for the safe and effective encryption of both text and image data. A HASH ...