This is not about replacing Verilog. It’s about evolving the hardware development stack so engineers can operate at the level of intent, not just implementation.

Work at every level of hierarchy, all way up to the complete SoC Interconnect signals that pass up and down through levels of hierarchy Generate bus “widgets” such as bridges, converters, aggregators, ...

This is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working ...

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