IEEE

Hardware Implementation of Systolic Array Architecture using 4:2 Compressor Approximate Multiplier for Image Processing Operations

Abstract: This research presents an innovative FPGA implementation of a $128 \times 128$ convolution systolic array architecture, optimized for image processing applications. The core of this design ...
IEEE

A 16×16 High-Utilization Systolic Array Hardware Accelerator for Long-Sequence Flash-Attention Computation in Transformer

Abstract: This paper presents a Flash-Attention accelerator design methodology based on a 16×16 high-utilization systolic array architecture for long-sequence Transformer applications. By ...