IEEE

A 37.5fs-rms Jitter and −254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset

Abstract: The revolution of communication protocols beyond 5G raises more and more stringent phase noise (PN) requirements on the local oscillator (LO) [1]. Sampling PLLs (SPLLs) have gained ...
IEEE

A 55.8-to-64.2GHz, $58.3\text{fs}_{\text{rms}}$-Jitter, $-250.2\text{dB-FoM}_{\mathrm{J}}$ Fractional-N Cascaded PLL in 28nm CMOS

The 2 nd -stage sub-sampling PLL features a 0.82mW switched capacitor frequency-to-voltage converter-based FLL, addressing a harmonic lock issue without a power-hungry mmWave frequency divider. Its ...