IEEE

Hardware Implementation of Systolic Array Architecture using 4:2 Compressor Approximate Multiplier for Image Processing Operations

Abstract: This research presents an innovative FPGA implementation of a $128 \times 128$ convolution systolic array architecture, optimized for image processing applications. The core of this design ...
IEEE

Low Power Systolic Array AI Accelerator with AXI MicroBlaze Co-Design on Artix-7

Abstract: This work proposes a compact, energy-efficient systolic array accelerator optimized for real-time edge AI workloads, implemented on the Xilinx Artix-7 FPGA (Basys-3 board). Unlike existing ...
SiliconANGLE

Chip startup MatX raises $500M to speed up large language models

MatX Inc., a chip startup founded by former Google LLC engineers, has raised $500 million in funding to bring its first product to market. Jane Street and Situational Awareness led the Series B ...